The present invention relates to fabrication methods and resulting structures of a field effect transistor (FET), and more specifically, to forming pillars for heat dissipation and isolation in vertical FETs (VFETs).
A FET is a three-terminal device that includes a source, drain, and gate. Generally, a FET is fabricated with the source and drain formed on the same lateral level such that current flow, which is controlled by the gate in the channel region between the source and drain regions, is horizontal. In the efforts to scale complementary metal-oxide semiconductor (CMOS) technologies to 5 nanometers and below, non-planar FET architectures such as fin-type FETs (finFETs) and vertical FETs (VFETs) have been pursued. In a finFET, the source, drain and channel regions are built as a three-dimensional fin, which serves as the body of the device. The gate electrode is wrapped over the top and sides of the fin, and the portion of the fin that is under the gate electrode functions as the channel. In a VFET, the channel is also formed in a three-dimensional fin. However, the gate in a VFET extends along and/or around the vertical sidewalls of the fin. As a result, current flow in the channel region is vertical rather than horizontal.